At sub-20 nm critical dimensions, pattern collapse of FinFET's and dielectric stacks during wet clean and dry has become a major problem in semiconductor manufacturing processes. The conventional theory of pattern collapse implicates high capillary forces during rinse and dry as major contributors leading to the collapse phenomenon. However, other chemical and substrate properties may play an important role as well, namely, liquid surface tension and viscosity, substrate mechanical strength, pattern density and aspect ratio, and cleaner chemistry damage to substrate surfaces.